6T-SRAM 4X4 Memory Bank (45nm)

Objective

Design a 4×4 6T Static Random Access Memory (SRAM) bank in 45 nm CMOS using schematic capture, layout implementation, and post-design simulation. The work includes the design of the SRAM cell and its supporting circuitry, including precharge, write, and sense-amplifier blocks. 

The project evaluates the maximum achievable read and write operating frequency of the SRAM bank, identifies the circuit block that limits high-speed operation, and measures the associated read and write energy. 

A final goal is to achieve a compact layout with minimal area while maintaining correct functionality.