Bemnet's EE Portfolio

👋 I'm Bemnet Tefera.

Incoming Analog/RF IC Design Engineer @Cadence.

Actively designing power/performance/area optimized high-speed Analog/Mixed circuits.

Blocks designed (45nm,130nm,180nm): Op-Amp, SAR-ADC, Bandgap, PLLs, DAC, Sample and Hold.

Skills: Cadence Virtuoso ADE, C/C++, Linux/Unix, Verilog-A, MATLAB, Python, Ngspice, Xscheme, IP Migration, Corner Analysis, Monte Carlo, DRC/LVS/PEX, Floor Planning

Fun activities: Philosophy/History, Classical Guitar, Weight lifting, Cycling, Jazz.

Projects

Drift and Noise Resilient Mixed-Signal Back End for On-Chip Magnetic Field Sensing (45nm)
(Analog/Mixed IC, ADC, PVT, Monte-Carlo)

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Standard Cell Design: Inverter, NAND2, NOR2, MUX2 in (45nm-Node)
(Analog/Mixed IC, ADC, PVT, Monte-Carlo)

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Smart HVAC Monitoring and Correction System
(Leak-Lock)
(Embedded Systems, C++, Signal Integrity)

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True Random Number Generation Via Voltage controlled Magnetic Anisotropy using MTJs
(Analog Circuit, PCB, Signal Integrity)

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Webcam Embedded Circuit Design
(Embedded Systems, C++, Signal Integrity)

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Bandgap Reference IC Design (45nm)
(Analog/Mixed IC, ADC, PVT, Monte-Carlo)

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