Abstract

This project presents a drift and noise resilient mixed-signal back-end architecture for on-chip magnetic field sensing. It puts together a Verilog-A Hall effect model, a low-noise analog front end, and a digitally calibrated signal processing chain. The analog subsystems, implemented in a GPDK 45nm technology, provide an 8-bit SAR ADC shared across the three sensor axes through a 3:1 analog multiplexer. To combat offset drift, temperature-dependent gain error, and flicker noise inherent in Hall and MTJ-based sensors, the digital backend performs startup calibration, real-time oversampling, exponential moving average drift tracking, and tri-axis vector assembly and single-pin serialized output. The result is a compact and fully integratable magnetic sensing solution that maintains long term accuracy and stability under environmental and device-level variations, allowing for robust operation in SoC-Embedded sensor platforms. 

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