Professional Experience
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Cadence Design Systems (San Jose, CA) Analog IC Design Intern (May 2025 – Aug 2025)
- Migrated a complete 8-bit SAR ADC pipeline from 45 nm to 130 nm technology as part of a 7-member team.
- Designed and laid out a high-speed two stage op-amp in Virtuoso, achieving robust stability across all PVT corners.
- Optimized a Sample and Hold circuit for sub-mV hold offset and 800 ps aperture time, improving ADC performance.
- Debugged SKY130 PDK standard-cell issues and proposed a fix by adjusting the DSPF file for accurate extraction.
Physical Electronics Research Laboratory (Evanston, IL) Research Design (April 2024 – Present)
- Investigated magnetic tunnel junctions for true random number generation via voltage controlled magnetic anisotropy.
- Designed a 10 MHz MTJ readout PCB with fast comparators and low-noise biasing for 200 million bits per sec.
- Improved random bit quality by 6% with linear feedback shift registers to meet NIST statistical standards.
- Validated bitstream randomness using the full NIST Statistical Test Suite across multiple datasets.
McCormick School of Engineering (Evanston, IL) Teaching Assistant (Mar 2024 – May 2025)
- Mentored 300+ students in electronics fundamentals, from Kirchhoff’s laws to Signals and Systems analysis.
- Facilitated lab sessions with ESP32 firmware coding, strengthening students’ practical understanding of electronics.
- Trained students on soldering, oscilloscopes, and common ECE lab equipment to build essential hardware skills.
- Provided individualized support and tutoring to help students master complex topics and succeed in coursework.
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